The F Architecture

The exact details of the F architecture are not yet all nailed down, but here are some of the basics:

• 64-bit datapath and address space
• Speculative and parallel execution pipelines
• Three cache levels:
  • L0: 8KB, 4-ported, line lockable - internal
  • L1: 64KB data plus 64KB intruction (dual ported, line lockable) - internal
  • L2: > 1MB (possibly!) - external (on motherboard)
• Instead of general-purpose registers, use "virtual registers" which correspond to locations in memory, as specified by memory window registers. Thus we get the advantages of a memory-to-memory architecure without the huge instruction sizes and slow access.
• NUMA-style multiprocessing (not Intel SMP, which is proprietary)
• FPU design is currently in flux, but is currently planned to be internal (the diagram below is now incorrect)

Napkin drawing cleaned up by Sean

You'll find some more details in The Freedom CPU Architecture and F-CPU Architecture: Register Organization.

Last updated September 11 1998 00:32:12 AM. Copyright 1998 The F-CPU Project. About This Site | Mirrors | Feedback