#This file was created by LinuxDoc-SGML
#(conversion : Frank Pavageau and Jose' Matos)
\lyxformat 2.15
\textclass linuxdoc
\language default
\inputencoding default
\fontscheme default
\papersize Default
\paperfontsize default
\spacing single
\secnumdepth 3
\tocdepth 3
\paragraph_separation indent
\defskip medskip
\quotes_language default
\quotes_times 2
\paperorientation portrait
\papercolumns 1
\papersides 1
\paperpagestyle default
\layout Title

\added_space_top vfill \added_space_bottom vfill
Estimating final end-user price of the F1 CPU 
\layout Author

Andrew D. Balsa 
\layout Date

August 1998 
\layout Abstract

An estimate of the end-user price of the F1 CPU. GNU/GPL
\layout Standard

\begin_inset LatexCommand \tableofcontents
\end_inset
\layout Section

Introduction 
\layout Standard

Although I am not an experienced cost analyst for the microprocessor industry, I do have a few years of university studies on my 
shoulders, and many years of experience in the microprocessor industry. 
Also keep in mind that actual chip fabrication costs are closely guarded secrets by all the major players in this industry. I only 
have some rough data and estimates published in industry magazines. I don't have (yet) any price quotes from foundries. 
\layout Standard

So: we'll only have final prices in Q4 1999, and the person in charge of watching foundry performance for our first F1 batches will 
work out better estimates than these, by then. 
\layout Standard

But roughly, and with a safety margin, the estimated end-user price of the F1 CPU in Q1 2000 will be around $ 100. This price 
includes a safe anti-static packaging, and is FOB our main distribution center which will probably be in the US. We may 
arrange to have a European distributor and a Hong-Kong distributor. 
\layout Section

Hypothesis 
\layout Enumerate
Projected die area of the F1 CPU: 122 mm2 (11 x 11 mm die). This hypothesis is justified by our transistor count estimate: 
roughly, comparing the F1 to the original Cyrix 6x86. The 6x86 at 0.5 micron 5-layer was 3.4 million transistors, die area was  
14.5 x 14.5 mm. We want to pack 10 - 11 million transistors in a 11 x 11 mm die using 0.25 micron 5 layer technology. And our chip 
will have a much higher percentage of transistors in the caches, compared to the 6x86 (the caches have a highly regular pattern, 
and so take less space than the irregular logic). The 10-11 million transistors can be divided as follows: 6-7 million transistors 
for the caches, 4-5 million for the rest... 
Similar comparisons with the IDT/Centaur C6 and the AMD K6 (both the "old" 0.35 micron version and the new 0.25 micron version) lead 
to the same conclusion: 10-11 million transistors is OK for a 122 mm2 die using 0.25 micron 5-layer technology and the cache sizes 
that we have chosen. 
\layout Enumerate
Packaging similar to the Intel Celeron. We are still working on this idea, but it seems the Celeron packaging (basically a PII 
without the cache chips and without the plastic/metal casing) would be the ideal solution. Something similar can be worked on for 
the Super 7 motherboards (except we don't need the L2 cache chips and external logic). Mechanical drawings available shortly on the 
F-Project Web site. These two form-factors already have widely available motherboards, mounting hardware and cooling solutions. 
Both provide 100MHz FSB, AGP video cards, efficient motherboard chipsets and well-known bus interfaces. 
\layout Enumerate
Roughly the cost structure for the dies described in Hennessy and Patterson, "Computer Architecture", 2nd Ed., Chapter 1 (there 
is some data found in the exercises, too; BTW I found a mistake at the end of paragraph 2 on page 63, it should say "at most" 
instead of "at least"; H&P's editors owe me $1). 
\layout Enumerate
8-inch wafer costs around $ 3.500 in year 2000. This is based on data I had collected in Q3 and Q4 1997 for 0.5 and 0.35 micron 
5-inch wafers, it is possible (and even probable) that costs may be much lower than that in 2000. Right now there is worldwide fab 
overcapacity, silicon prices are really low. 
\layout Enumerate
Our first F1 batch will count around 5.000 - 10.000 good CPUs. More on this below. 
\layout Enumerate
Good masks. Obviously, if the masks are flawed... we could try to sell the dies as key rings, souvenirs, etc. ;-) 
\layout Section

Calculation 
\layout Standard

Our 122 mm2 die area gives us 200 dies/8-inch wafer (see an example of such a wafer on Hennessy and Patterson, 
page 11). 
\layout Standard

Roughly, die yield = 0.5 for our 122 mm2 5-layer 0.25 micron CPU (H&P, page 13, updated to reflect better fabs in the year 2000). 
\layout Standard

We also assume wafer yield = 95%, final test yield = 95%. Testing costs of $500/hour, 20 seconds/CPU. All these are from H&P. 
\layout Standard

Packaging costs = $25-50. This includes the BGA packaging for the F1 chip itself, the SMD EEPROM for the F1 x86 compatibility BIOS, 
a few ssi SMD glue logic chips, decoupling caps and the PCB (4 layer? 6 layer?). 
\layout Standard

The calculation is really simple then. 
\layout Standard

Wafer cost: $ 3.500. Good dies: 200 x 0.5 (die yield) x 0.95 (wafer yield) = 95 dies /wafer. 
\layout Standard

Die cost is now: $ 3500 / 95  = $ 36.85. Testing costs: 500 / 180 (dies tested per hour) = $ 2.80. 
\layout Standard

So, die + packaging costs: $ 36.85 (good die) + $ 2.80 (testing) + $ 50 (packaging) = $ 89.65. 
\layout Standard

Final cost: $ 89.65 / 0.95 (final test yield) + $ 2 (anti-static packaging)  = $ 96.40. 
\layout Standard

Shipping to the US distribution center accounts for the remaining $ 3.60. :-) 
\layout Standard

Roughly, following H&P, this gives us a unit cost of $75-100/good CPU (depending on the cost of packaging), tested, boxed in 
anti-static packaging and shipped to the US. Compare that to the estimated initial selling price of the Merced: $ 5.000! Or to the 
actual selling price of Intel Xeon processors (which are just glorified Celeron processors) of around $ 2.000. Also compare that to 
the $80 selling price of the 266 MHz Celeron... 
\layout Standard

Yes, it can be done. :-) 
\layout Standard

\the_end